IDDQ Test: Sensitivity Analysis of Scaling

نویسندگان

  • Thomas W. Williams
  • Robert H. Dennard
  • Rohit Kapur
  • M. Ray Mercer
  • Wojciech Maly
چکیده

While technology is changing the face of the world, it itself is changing by leaps and bounds; there is a continuing trend to put more functionality on the same piece of silicon. Without major changes in the CMOS technology, it has been shown that the scaling of devices has signi cant impact on the e ectiveness of Iddq testing. The sensitivity of Iddq testing to individual device parameters is studied. It will be explained how Iddq testing becomes increasingly ine ective in the scaled product with respect to most parameters and can be improved with others.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

A High Performance IDDQ Testable Cache for Scaled CMOS Technologies

Quiescent supply current (IDDQ) testing is a useful test method for static CMOS RAM and can be combined with functional testing to reduce total test time and to increase reliability. However the sensitivity of IDDQ testing deteriorates significantly with technology scaling as intrinsic leakage of CMOS circuits increases. In this paper, we use a design technique for high-performance cache, which...

متن کامل

Guest Editors' Introduction: Defect-Oriented Testing in the Deep-Submicron Era

0740-7475/02/$17.00 © 2002 IEEE September–October 2002 CMOS IC SCALING increases device/interconnect density to allow more logic on a die at higher clock rates, enhancing overall performance. Improvements in process technology enable integration on a single die of circuits with different functions that require distinct manufacturing process steps. With added constraints of reduced time to marke...

متن کامل

Wafer Signature Analysis

Continuous scaling of transistor geometries increases leakage current exponentially. This makes differentiating faulty and fault-free chips extremely difficult. The concept of wafer signature is proposed. A wafer signature is obtained by sorting all IDDQ readings on a wafer for a vector. A break or jump in the wafer signature is considered to indicate defective chips. The use of wafer signature...

متن کامل

Current ratios: a self-scaling technique for production IDDQ testing

The use of a single pass/fail threshold for IDDQ testing is unworkable as chip background currents increase to the point where they exceed many defect currents. This paper describes a method of using " current signatures " which uses only simple comparisons on the tester, and which automatically scales with process variations which give a wide range of background currents. Dynamic thresholds ar...

متن کامل

NCR: A Self-scaling, Self-calibrated Metric for IDDQ Outlier Identification

IDDQ testing is an important component of a test suite. However, increasing leakage current values with each technology node render single pass/fail limit setting approach obsolete. This is further worsened due to increasing process variations and discriminating faulty and fault-free chips is becoming increasingly difficult. In this paper we evaluate a metric that uses wafer-level spatial infor...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 1996